PROCESS CP329V Small Signal Transistor NPN- Silicon Darlington Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER 15,980 PRINCIPAL DEVICE TYPES CMPTA29 CZTA29 MPSA29 EPITAXIAL PLANAR 27 x 27 MILS 7.1 MILS 4.2 x 4.2 MILS 4.3 x 4.3 MILS Al Au - 30,000A - 13,000A 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (20 -January 2006)
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